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74AC377 * 74ACT377 Octal D-Type Flip-Flop with Clock Enable
November 1988 Revised March 2005
74AC377 * 74ACT377 Octal D-Type Flip-Flop with Clock Enable
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Features
s ICC reduced by 50% s Ideal for addressable register applications s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s Outputs source/sink 24 mA s See 273 for master reset version s See 373 for transparent latch version s See 374 for 3-STATE version s ACT377 has TTL-compatible inputs
Ordering Code:
Order Number 74AC377SC 74AC377SJ 74AC377MTC 74AC377MTCX_NL (Note 1) 74AC377PC 74ACT377SC 74ACT377SJ 74ACT377MTC 74ACT377PC Package Number M20B M20D MTC20 MTC20 N20A M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names D0-D7 CE Q0-Q7 CP Description Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS009961
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74AC377 * 74ACT377
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs Operating Mode CP Load `1' Load `0' Hold (Do Nothing) Outputs Dn H L X X Qn H L No Change No Change CE L L H H

X
H HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74AC377 * 74ACT377
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r50 mA r50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD ICC (Note 5) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1 V V
IOH IOH IOH IOUT VIN
12 mA 24 mA 24 mA (Note 3)
50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 3) VCC, 1.65V Max 3.85V Min VCC or GND
0.44 0.44 0.44 V
IOL IOL IOL VI
r 0.1
r 1.0
75
PA
mA mA
GND VOLD VOHD VIN
75
40.0
PA
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
3
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74AC377 * 74ACT377
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 7) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36
25qC
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V IOUT VIN
50 PA
VIL or VIH
V
IOH IOH
24 mA 24 mA (Note 6)
50 PA VIL or VIH 24 mA 24 mA (Note 6) VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC
V
IOUT VIN
V
IOL IOL
r0.1
r1.0
1.5 75
PA
mA mA mA
VI VI
VOLD VOHD VIN or GND
75
40.0
PA
Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC Symbol Parameter (V) (Note 8) fMAX tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn
Note 8: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA Min 90 140 3.0 2.0 3.5 2.5
25qC
Typ 125 175 8.0 6.0 8.5 6.5 13.0 9.0 13.0 10.0 Max
TA
40qC to 85qC
Max 75
Units
Min 125 1.5 1.5 2.0 1.5
3.3 5.0 3.3 5.0 3.3 5.0
MHz 14.0 10.0 14.5 11.0 ns ns
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74AC377 * 74ACT377
AC Operating Requirements for AC
VCC Symbol Parameter (V) (Note 9) tS tH tS tH tW Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW CE to CP Hold Time, HIGH or LOW CE to CP CP Pulse Width HIGH or LOW
Note 9: Voltage Range 3.3 is 3.0V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 3.5 2.5
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
Guaranteed Minimum 5.5 4.0 0 1.0 6.0 4.0 0 1.0 5.5 4.0 6.0 4.5 0 1.0 7.5 4.5 0 1.0 6.0 4.5 ns ns ns ns ns
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
2.0 1.0
4.0 2.5
3.5 2.0
3.5 2.5
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 10) fMAX tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 140 3.0 3.5
25qC
50 pF Typ 175 6.5 7.0 9.0 10.0 Max
TA
40qC to 85qC
CL 50 pF Max MHz 10.0 11.0 ns ns Units
Min 125 2.5 2.5
5.0 5.0 5.0
AC Operating Requirements for ACT
VCC Symbol Parameter (V) (Note 11) tS tH tS tH tW Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW CE to CP Hold Time, HIGH or LOW CE to CP CP Pulse Width HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V r 0.5V
TA CL Typ 2.5
25qC
50 pF
TA
40qC to 85qC
CL 50 pF Units
Guaranteed Minimum 4.5 1.0 4.5 1.0 4.0 5.5 1.0 5.5 1.0 4.5 ns ns ns ns ns
5.0 5.0 5.0 5.0 5.0
1.0
2.5
1.0
2.0
Capacitance
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Typ 4.5 90.0 Units pF pF VCC VCC OPEN 5.0V Conditions
5
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74AC377 * 74ACT377
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74AC377 * 74ACT377
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
7
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74AC377 * 74ACT377
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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8
74AC377 * 74ACT377 Octal D-Type Flip-Flop with Clock Enable
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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